1. Field of the Invention
This invention relates to a video signal reproduction circuit for reproducing a chrominance signal used for a VTR for home (consumer) use, and more particularly to a video signal reproduction circuit for NTSC or
formats in which the number of elements is reduced.
2. Description of the Related Art
FIG. 1 shows a conventional structure of a circuit for reproducing a chrominance signal which has been converted into a low frequency band and recorded on a magnetic tape (not shown). A signal read out from the magnetic tape is input through an input terminal 1 to a low pass filter (LPF) 2 for extracting only a frequency component of 629 kHz in the case of NTSC format or a frequency component of 627 kHZ in the case of PAL format, which is then input to an automatic chroma control circuit (ACC circuit) 3 for level adjustment.
The level adjusted chrominance signal is applied to a first frequency conversion circuit 4, and is converted to a frequency of 3.58 MHz for NTSC format or to a frequency of 4.43 MHz for PAL format, which is then fed via a band pass filter (BPF) 5 to a comb filter 6 to any remove noise components before being output from the output terminal 7.
The chrominance signal output from the BPF 5 is also applied to a burst gate circuit to extract only a burst component, which is then fed to an automatic phase control (APC) circuit 9. In the APC circuit 9, the phase of the burst signal is compared with the phase of an oscillation signal output from a fixed type oscillator 10 (3.58 MHz or 4.43 MHz). The difference between the phases of the two signals is output from the APC circuit as a comparison error voltage, and is applied to a VCO 11 to control the oscillation frequency of the VCO 11 (320 fH for NTSC and 321 fH for PAL: fH is a horizonal synchronizing frequency).
The output of the VCO 11 having a frequency of 320 fH or 321 fH is applied to a phase recovery circuit (a phase shifter) 12 to generate four signals (40 fH for NTSC, 40.125 fH for PAL), the phases of which are shifted with respect to one another by 90 degrees in response to a horizontal synchronizing signal, input via a terminal 13 and having a frequency of fH, and a color rotary pulse from a terminal 14. The phase recovery circuit 12 is switched to successively output four signals every 1 H period (H: horizontal synchronizing period), thereby recovering the phase of the chrominance signal which was converted to a low frequency band and recorded on the magnetic tape.
The output from the phase recovery circuit 12 (40 fH or 40.125 fH), as well as an oscillation signal (3.58 MHz or 4.43 MHz) from the oscillation circuit 10, are supplied to a second frequency conversion circuit 15, in which an addition and a difference of the two signals (from the phase recovery circuit 14 and the oscillation circuit 10) are obtained. Only the addition component of the two signals is supplied through a band pass filter 16 to the first frequency conversion circuit 4, thereby obtaining 3.58 MHz (for NTSC format) or 4.43 MHz (for PAL format) signal.
JP-A-60-253395 (Japanese Patent Laid-Open No. Sho 60-253395) discloses digital recovering of the phase of a low frequency band chrominance signal which is supplied to the first frequency conversion circuit. Such an NTSC format digital reproducing circuit for a chrominance signal is shown in FIG. 2. The chrominance signal is input via an input terminal 100 to a low pass filter 102 to extract a chrominance signal of less than 630 Hz (e.g. 629 kHz), which is then applied to the A/D converter 103. Meanwhile, a horizontal synchronizing signal fH is applied via an input terminal 104 to a multiplier 105 and is multiplied by 320 in order to sample a 40 fH Hz chrominance signal for every 45 degrees. The output from the multiplier 105 having a frequency of 320 fH is supplied, as a clock pulse, to the A/D converter 103. The digitally converted chrominance signal (629 kHz) is input to the 1 H memory 106 consisting of 6 bit RAM. This signal is written in the address designated by the address counter 107, and is read out after a 1 H (horizontal synchronizing signal) period by the readout address counter 108.
The write address counter 107 is reset by a horizontal synchronizing signal fH, and counts a signal having a frequency of 320 fH to designate the address in the 1 H memory 106.
The readout address counter 108 is reset by an output of the phase shift commander 109, and counts a 320 fH signal from the multiplier 110 to designate the readout address of the 1 H memory 106.
The VXO 111 oscillates at (455/2)fH=3.58 MHz, and the oscillation signal is divided by 2/445 by the divider 112 and multiplied by 320 by the multiplier 110 to provide a signal having a frequency of 320 fH.
Readout timing of the 1 H memory 106, which is responsive to the output of the phase shift commander 109, is shifted every 1 H by a 1/4 cycling period of the low frequency chrominance signal (that is, 90.degree.), thereby carrying out the phase recovery of the low frequency chrominance signal.
The phase recovery processing is described in more detail with reference to FIG. 3 which shows write/readout clock and the corresponding waveforms. In this figure, the low frequency chrominance signal is in the odd numbered field where the phase is delayed by 90 degrees every 1 H , and the explanation of the phase shift in the even numbered field will be omitted. In FIG. 3, signal (a) is a write clock for the 1 H memory 106, while signal (c) is a readout clock for the 1 H memory 106. Signal (b) is an input digital signal to the 1 H memory 106, and signal (d) is an output digital signal of the 1 H memory 106. The signals (b) and (d) are depicted in analogue form in the figure for convenience of the explanation.
During a 1 H period where the phase shift amount is 0.degree., signal (b) is successively written in the 1 H memory in response to a signal (a) (i.e. writing clock) as from the address 0 of the 1 H memory 106. Readout of this signal, which has 0.degree. of phase shift, is carried out by the readout counter 108 which is reset to "0" in response to the output of the phase shift commander 109. More particularly, data is read out responsive to the clock represented as signal (c) as from the address 0 of the 1 H memory 106.
Then, during the next 1 H period, signal (b) which is delayed by 90.degree. is successively written into the 1 H memory 106 from the address 0. The data is read out by shifting the phase by 90.degree. to recover the proper phase. More particularly, the readout counter 108 is preset to "2" by the phase shift commander 109 to read out the data from the address 2, as is shown by signal (c). Thus, the phase of the signal is advanced by 90 degree by reading out from the address 2, thereby obtaining a continuous original signal, without discontinuity between the first 1 H period and the next 1 H period, as is shown by signal (d).
In the same manner, during the next 1 H period, the signal (b) which is delayed by 180.degree. is written from the address 0, and the data is read out as from the address 4 to advance the phase by 180.degree., thereby recovering the continuous original signal. Setting the starting of the readout address is carried out by the address counter 108 which is reset to a predetermined value in response to the output of the phase shift commander 109. As a result, the phase recovered low frequency chrominance signal is generated from the 1 H memory 106, as is depicted by signal (d).
The thus phase recovered low frequency chrominance signal is applied to the comb filter 115 consisting of the 1 H memory 113 and the adder 114 for removing any crosstalk components, and is further applied to the D/A converter 116 to be converted to the analogue signal, which is then fed to the main converter 117 to be recovered to a 3.58 MHz chrominance signal.
However, in the structure shown in FIG. 1, since the four signals generated by the phase recovery circuit 12, the phases of which are shifted from one another by 90.degree., are applied via the second frequency conversion circuit 15 to the first frequency conversion circuit 4, a band pass filter 16 of complicated structure is required. Furthermore, the number of elements is increased because of the structure having two frequency converters.
On the other hand, in the structure shown in FIG. 2, the chrominance signal converted to a low frequency band is directly subjected to the phase recovery processing, and therefore, the band pass filter 119 of simple structure is only provided between the main converter 117 and the sub converter 118. However, in this structure, the phase recovery is carried out by delaying (or advancing) the readout timing from the memory, and the low frequency chrominance signal is shifted by 45.degree. between the adjacent two 1 H periods, which results in insufficient removal of the crosstalk in the comb filter 115. This is indicated by the dashed lines A and B at the end of the 1 H period of +90.degree. and +180.degree.. In other words, in the readout operation by clock signal (c), no data is read out for the last time period of the 1 H period, which corresponds to the time period which has been skipped at the first portion of the 1 H period, resulting in lack of data. Such a time period lacking data is generated every perpendicular period, causing a deterioration of image quality.
The reason why the phase error of 45.degree. is caused will now be described. Time lag T1 between the input and output of the 1 H memory 113 is originally 1/fH . However, when 1/4 period (.DELTA.T=(1/4) * (1/40 fH ) 1/160 fH ) is shifted, the time lag T2 becomes (1/fH ) +(1/160 fH ) (161/161 fH ). Then, the transfer function H (.omega.) is represented by the following equation. ##EQU1## where, s=j.omega.. This equation (1) can be transformed to; ##EQU2##
The equation (2) is further transformed using Euler's formula as follows. ##EQU3##
By substituting 2.pi.fH for .omega., the following equation is obtained. EQU .vertline.H(.omega.)=.vertline.2 cos (40 .pi.+.pi./4).vertline.(4)
".pi./4" in the equation (4) indicates that the notch of the comb filter for the interleaved chorominance signal is offset by .pi./4 in the vicinity of 629 KHz, which is shown in FIG. 4. The solid line indicates ideal frequency characteristics of a comb filter, wherein the maximum level of signal can pass at 629 KHz (=40 fH ) and a luminance component is removed at attenuation points generated symmetrically about 629 KHz at cycles of fH (horizontal synchronizing frequency).
On the contrary, when a phase difference of 45.degree. is caused, the frequency characteristic of the comb filter is shifted as is indicated by dashed line, which means that a 629 KHz signal can not pass at its maximum level nor can removal of luminance component be achieved.